1. Field of the Invention
The present invention relates to an accessing scheme in a block access memory and, more specifically, it relates to a method and apparatus for driving a word line in a block access memory which is accessed by block unit.
2. Description of the Prior Art
Recently, in a large capacity MOS RAM (random access memory constituted by MOS transistors), as it comes to be implemented in higher integration, it has been desired to enhance the data input/output rate. The method for enhancing the data input/output rate is mainly constituted by the following two methods.
(1) The data input/out rate is increased by making the MOS RAM with multi bit structure. In this case, the degree of integration is sacrificed both in the chip level and the package level due to the increase of the area of the portions for the parallel operation in the chip and to the increase of the number of the terminals in the package.
(2) Multi bits are serially inputted/outputted at high speed by providing shift registers respectively at the data input/output portions. In this case, the disadvantages shown in the above described method (1) can be eliminated except the increase of the chip area by the arrangement of the shift registers.
In order to draw much advantage from the method (2), the following method is proposed.
(2') The number of the terminals in the package is reduced by serially inputting control signals from one terminal and by serially carrying out address input and data input/output at one terminal.
By incorporating the methods (2) and (2'), the packaging density can be significantly enhanced and the data input/output can be carried out at high speed.
FIG. 1 shows a schematic structure of the above described semiconductor memory device in which address input and data input/output are carried out serially through one terminal. In FIG. 1, a data input/output terminal 1, a clock input terminal 2, a supply terminal 3 to which the supply voltage Vcc is applied, and a ground terminal 4 which is connected to the ground potential Vss are provided as the external terminals (terminals which are connected to the external circuits). The data input/output terminal 1 receives a write data input to the memory cells provided in the device, a read data output from the memory cells, a row address input and a control for designating the operation mode. The clock input terminal 2 receives a clock signal CLK for providing the operation timing of each of the portions in the device.
The memory cell array storing the information is divided into a plurality of blocks (four blocks in FIG. 1) B1, B2, B3 and B4. In each of the blocks B1 to B4, provided are a plurality of memory cells MC arranged in rows and columns each of which storing information, a plurality of word lines WL for selecting one row of the plurality of memory cells MC and a plurality of bit lines BL to which one column of the plurality of memory cells MC is connected. In FIG. 1, only one word line WL and one bit line BL are shown for the simplification of the drawing. The two bit lines shown in the figure illustrate that the bit line has the folded bit line structure and is constituted by a bit line pair on which complementary information appears. Each memory cell MC usually has the structure of one transistor and one capacitor. Corresponding to each of the memory blocks B1 to B4, sense amplifiers SA1, SA2, SA3 and SA4 are provided for detecting and amplifying the potential on the bit line which appears dependent on the information contained in the selected memory cell. The sense amplifiers SA1 to SA4 also has the function of data latch and, in addition, the sense amplifiers carry out the refresh operation of each memory cell.
In order to select one word line in response to externally applied address signals, a row decoder RD1 is provided for the blocks B1 and B2 while a row decoder RD2 is provided for the blocks B3 and B4.
A block selector for selecting one of the blocks B1 to B4 and an I/O shift register for reading/writing data into/from the block selected by the block selector are provided for carrying out data input/output. In FIG. 1, the block selector and the I/O shift register are shown as one structure block 5.
As the data input/output path, provided are a data output buffer 6 which receives the information contained in the memory cells selected by an external address through the block selector +I/O shift register 5 and transmits the same to the serial/parallel conversion circuit 10; a data input buffer 7; which serially receives the serial data applied from the data input/output terminal 1 through the serial/parallel conversion circuit 10 and transmits the same to the block selector +I/O shift register 5; a control signal generation circuit 8 which receives a control applied through the data input/output terminal 1 through the serial/parallel conversion circuit 10 and generates a block selection signal, a sense amplifier activating signal, a data output buffer activating signal, a data input buffer activating signal, a row decoder activating signal and a row address buffer activating signal; a row address buffer 9 which receives a row address applied through the data input/output terminal 1 through the serial/parallel conversion circuit 10 in parallel and transmits the same to the row decoders RD1 and RD2; and a serial/parallel conversion circuit 10 which operates in response to a clock signal CLK applied through the clock input terminal 2, serially receives a signal applied from the data input/output terminal 1 and applies in parallel the same to the data input buffer 7, the control signal generation circuit 8 or to the row address buffer 9 and which transmits the read data from the data output buffer 6 to the data input/output terminal 1 as the output data.
In FIG. 1, each of the blocks B1 to B4 has a capacity of 256k bits of 256 row.times.1024 column, as an example.
The operation will be briefly described. The external row address applied through the data input/output terminal 1 is applied to the row address buffer 9 through the serial/parallel conversion circuit 10 and is applied to the row decoders RD1 and RD2 under the control of the control signal generation circuit 8. In the row decoders RD1 and RD2, the unit row decoder designated by the row address is selected out of the unit row decoders included in the row decoders RD1 and RD2 in response to the applied row address, and the word line connected to the selected unit row decoder is activated and the potential of the selected word line rises. Consequently, the stored data contained in the memory cell group (for one row) connected to the selected word line respectively appear on the bit line as the signal potential. The signal potential appeared on the bit line is detected and amplified by a sense amplifier which is activated in response to the control signal from the control signal generation circuit 8. As a result, the potential corresponding to the information "1" or "0" contained in the memory cell connected to the selected word line is established in each bit line. On this occasion, the sense amplifiers are activated only in the block to which the selected word line belongs.
In reading data, the read data, which are detected and amplified by the sense amplifier of the block to which the selected word line belongs out of the sense amplifiers SA1 to SA4, are transmitted and latched at the shift register provided corresponding to the blocks. Thereafter, one block is selected in response to a block select signal generated by the control signal generation circuit 8, the shift register corresponding to that block is activated and the data latched in the shift register are serially read according to the shifting operation of the activated shift register, and are outputted serially as the output data through the data output buffer 6, serial/parallel converting circuit 10 and the data input/output terminal 1. In data writing, in the reverse manner, the serial data stream applied through the data input/output terminal 1 is applied to the data input buffer 7 through the serial/parallel conversion circuit 10 and then is transmitted to the shift register provided corresponding to the block selected by the block selection signal and is latched therein. Thereafter, latched information is applied from this shift register to the bit lines through the activated sense amplifier and is written in the corresponding memory cells.
FIG. 2 is a diagram of waveforms showing the operation timing of the block access memory shown in FIG. 1. In FIG. 1, the operation timing for a certain 1 cycle is illustrated. Now, 1 cycle means the period from the reset operation to the next reset operation, and the reset operation is carried out if the data input/output terminal 1 is at "L" when the clock CLK input rises. When the reset operation is carried out, the memory cell array, the shift register and the serial/parallel conversion circuit 10 are reset (initialized). After completion of the reset operation, as long as the signal level at the data input/output terminal 1 is "H" level when the clock CLK rises, a certain operation cycle is continuously carried out and either control input, row address input, data input or data output is carried out through the data input/output terminal 1 when the clock CLK falls.
FIG. 3 is a table showing the relation between the operation mode and the control designating the operation of each operation cycle.
The 3 bit input (C0, C1, C2) applied at the start of each cycle is a control input and designates the basic operation of the succeeding cycle. The basic operation is defined as shown in FIG. 3, namely,
(1) row address set: the cycle in which following the 3 bit control input cycle, a row address is inputted on which an operation cycle designated by the control is carried out;
(2) read/refresh: the cycle in which detection and amplification of the memory cell data are carried out by the sense amplifier;
(3) write: the cycle in which writing into memory cells is carried out from the shift register through the sense amplifier and bit lines;
(4) serial input: the cycle in which the external input data applied through the data input/output terminal 1 is set in the shift register; and
(5) serial output: the cycle in which the information contained in the shift register is serially outputted to the data input/output terminal 1.
Therefore, one of the above described five operation cycles is selected by the combination of the value of the 3 bit control C0, C1 and C2. The data which appears at the data input/output terminal 1 following the 3 bit control will be as follows, dependent on each designated cycle:
(1) in the case of row address set: serial input of row address. If the memory cell array has the capacity of 1M bits and the number of word lines is 1024 ( =2.sup.10), then 10 bits are required for the row address and 10 clocks are required.
(2) and (3) in the case of read/refresh and write cycle: only the control input cycle is carried out and there is no relation with the data input/output.
(4) in the case of serial input: the input data applied to the data input/output terminal 1 are serially set in the shift register. The number of bits should be equal to the required number for setting the shift register and the corresponding number of clocks is required. For example, in the structure such as shown in FIG. 1, that is, each block comprises 256 row.times.1024 column, 1054 sense amplifiers are provided for the respective blocks, so that the shift register should store 1024 bits, requiring 1024 clocks.
(5) in the case of serial output: the data latched in the shift register is serially outputted in order from the first bit through the data output buffer 6 and the serial/parallel conversion circuit 10 to the data input/output terminal 1 successively. Therefore, in the case such as shown in FIG. 1, 1024 clocks are required as in the above described case (4), in order to read the selected data of one row (1024 bits).
As described above, the actual memory operation is carried out by incorporating five operation cycles constituted by the operation cycles (1) to (5); however, the block access memory structured as described above has the following disadvantages.
In the above described conventional block access memory, the memory operation is basically carried out by using one row of memory cells (block unit) as a unit (in the conventional block access memory shown in FIG. 1, 1024 bit serial input/output), and 1024 sense amplifiers are simultaneously activated for the selected one word line, so that an extremely large peak current flows as the bit lines are charged/discharged. This large peak current causes noise and leads to an error due to the fluctuation of the substrate potential and so on.
In order to avoid the error due to the above described large peak current, a method is known in which the number of the row decoder is increased and the word lines are divided so that the number of the sense amplifiers activated corresponding to one word line can be reduced. However, this method increases the chip area due to additional row decoders, so that it is not advantageous in increasing memory capacity. In addition, since it takes much time for inputting/outputting data serially, it is not suited for serial accessing.
As described above, in a conventional block access memory, the information contained in the memory cells connected to the selected one word line is read or written at one time, so that the sense amplifiers provided corresponding to the bit lines for one row are simultaneously activated, causing a large peak current associated with charge/discharge of the bit lines.
The structure in which data transfer is carried out simultaneously between the memory cells of one row of the RAM and the shift register is disclosed in R. O. Berg, U.S. Pat. No. 4,044,339 entitled "Block Oriented Random Access Memory", F. H. Dill et al., U.S. Pat. No. 4,541,075 entitled "Random Access Memory Having a Second Input/Output Port" and R. Pinkham et al., "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications", IEEE Journal of Solid-State Circuits Vol. SC-19, No. 6, December 1984. In the above mentioned prior art, the improvement in the data transfer rate is effected by the simultaneous transfer of the data for one row using a shift register; however, since the sense amplifiers of one row are simultaneously activated, there is another disadvantage that the peak current is large which flows when the sense amplifiers are activated. No means is disclosed in the prior art to solve this problem.